The present invention relates to a semiconductor integrated circuit device and a technique for manufacturing the same and, more particularly, to a technique which is effective if applied to a semiconductor integrated circuit device having a SRAM (i.e., Static Random Access Memory).
The SRAM, as acting as a semiconductor memory device, is equipped with memory cells a memory cell which is disposed at an intersection between a word line and a pair of complementary data lines and composed of a flip-flop circuit and two transfer MISFETs (i.e., Metal Insulator Semiconductor Field Effect Transistors).
The flip-flop circuit of the memory cell of the SRAM is constructed as an information storage unit for storing information of 1 bit. This flip-flop circuit of the memory cell is exemplified by a pair of CMOS (i.e., Complementary metal Oxide Semiconductor) inverters. Each of the CMOS inverters is composed of n-channel type drive MISFETs and p-channel load MISFETs. On the other hand, transfer MISFETs are of the n-channel type. In short, this memory cell is of the so-called “CMOS (i.e., Full Complementary Metal Oxide Semiconductor)” using the six MISFETs. Incidentally, the complete CMOS type SRAM, which is formed over the principal surface of the semiconductor substrate with the drive MISFETs, the load MISFETs and the transfer MISFETs, will be called the “bulk CMOS type SRAM”. This bulk CMOS type SRAM is disclosed, for example, on pp. 590 to 593 of IEDM (i.e., International Electron Device Meeting), Technical Digest, 1985.
In the SRAM of this kind, the paired CMOS inverters constituting the flip-flop circuit have their input/output terminals crossly connected with each other through a pair of wiring lines (as will be called the “local wiring lines”). One of the CMOS inverters has its input/output terminals connected with the source region of one of the transfer MISFETs, and the other CMOS inverter has its input/output terminals connected with the source region of the other transfer MISFET. One of the complementary data lines is connected with the drain region of one of transfer MISFETs, and the other complementary data line is connected with the drain region of the other transfer MISFET. With the individual gate electrodes of the paired transfer MISFETs, there is connected word lines, by which are controlled the ON/OFF of the transfer MISFETS. In the above-specified Publication, the local wiring lines are formed by a self-aligning silicide process. This silicide process per se is disclosed on pp. 118 to 121 of IEDM, Technical Digest, 1984.